This invention relates generally to electron image projection systems, and, more particularly, to techniques for the alignment and registration of successive lithographic layers on semiconductor devices produced in electron image projection systems. As is well known, electron beam lithography, in contrast to photolithographic techniques that employ light to define a desired pattern on a device, results in greatly improved resolution, and permits further reduction in the size of semiconductor devices. Photolithographic techniques are ultimately limited by the wavelength of the light source used.
There are two fundamentally different techniques of electron beam lithography used in the fabrication of semiconductors. First, in scanning electron beam systems, a single electron beam is deflected magnetically to impinge on desired portions of a target wafer. The beam "writes" on the wafer in somewhat the same way that an electron beam is used to form an image on a video screen.
The other technique is that of electron image projection, in which an entire pattern is projected onto the wafer as a large number of parallel electron beams. The basic approach used in electron image projection is well known. A photocathode mask, typically of glass coated with a mask pattern of titanium oxide and a thin layer of palladium over the mask pattern, is irradiated from its uncoated face by ultraviolet light. Those areas of the palladium not shielded by the titanium oxide emit electrons, which are accelerated toward the wafer by an electric field. Physical alignment of the mask and the wafer is extremely difficult, and alignment is usually accomplished by magnetically deflecting and rotating the projected electron image. Although electron image projection systems have been widely discussed in the literature and have been available for some years, they have not become widely accepted as production tools, principally because of the difficulties of achieving sufficient accuracy of alignment and registration of successive lithographic layers.
The term "alignment" has a special meaning as used in this specification, and in the integrated circuit field in general. It refers to the registration of special alignment marks on the wafer with corresponding features on a mask pattern being projected. For relatively large masks, the alignment of the marks does not necessarily ensure alignment of the entire image. Registration of other parts of a mask pattern, other than the alignment marks, is referred to as "overlay." The term "overlay accuracy" refers to the accuracy of registration of successive layers of an integrated circuit.
Electron image projection systems in the past have been able to achieve an alignment accuracy to submicron levels. However, the overlay accuracy has not been high enough for submicron imaging. In addition, the alignment marks that have to be used occupy a relatively large area of the wafer. This effectively restricts their use to single alignments per wafer exposure, unless significant areas of the wafer are set aside for alignment marks.
In scanning electron beam systems, alignment is typically achieved by detection of back-scattered or secondary electrons that emanate from alignment marks on the substrate or wafer, as a result of bombardment by the scanned electron beam. However, this approach cannot be effectively used for electron image projection systems, principally because the presence of strong electrical and magnetic fields co-axial with the original projection direction tend to confine secondary and back-scattered electrons to the substrate surface.
One prior approach to alignment for electron image projection systems is disclosed in U.S. Pat. No. 3,745,358 issued to Richard B. Firtz et al. At least two holes are formed in the wafer, and projected electron beams from the mask pass through the holes when there is perfect alignment. Detectors located beneath the holes sense the intensity of the electron beams, and appropriate control circuitry deflects the electron image to maximize output from the detectors. Although this approach was a significant improvement over the art, it does not provide the alignment sensitivity required for submicron overlay accuracy. Moreover, formation of the necessary holes in the wafers has practical difficulties, and is an additional step in the wafer production process.
U.S. Pat. No. 3,849,659 issued to Terence W. O'Keeffe discloses one approach to the use of back-scattered electrons for alignment in an electron image projection system. In O'Keefe's arrangement, several alignment marks are disposed about the periphery of the wafer, and function to back-scatter electrons toward detectors located outside the wafer periphery. Unfortunately, the technique permits the alignment marks to be located only at the wafer periphery. A back-scatter detector placed above the wafer would be in the path of the projected electrons and would distort the projected image. However, having the alignment marks placed only at the wafer periphery precludes the attainment of submicron overlay accuracy.
Another alignment technique that has been suggested involves the use of Brehmsstrahlung x-rays, and is described in a paper by Julian P. Scott, entitled "An Electron Image Projector with Automatic Alignment," IEEE Transactions on Electronic Devices, Vol. ED-22, No. 7, July 1975, pp. 409-13. Unfortunately, the detectors have to be located beneath the wafer and the x-rays are greatly attenuated by the silicon material of the wafer. Moreover, relatively large alignment marks are required, so that only a few sites on the wafer can be employed for alignment purposes, without sacrificing some of the area of the wafer available for fabrication of circuitry.
In present-day integrated circuit fabrication technology, an overlay precision of one micron in a 75 mm diameter chip has been achieved. This corresponds to a dimensional signal-to-noise ratio of approximately 1-2 parts in 10.sup.5. To achieve an overlay precision of 0.2 micron over a 100 mm diameter chip would require a dimensional signal-to-noise ratio of approximately two parts in 10.sup.6, or more than ten times the presently attainable overlay precision.
Unfortunately, overlay precision is limited by factors unrelated to the type of lithographic technique employed. Even with electron beam lithography and a highly accurate set of masks, overlay precision is still limited by the nature of the fabrication process steps that the wafer undergoes. Hot processing steps can induce anisotropic deformation of the wafer and its topology, and in some process steps there can be relative movement of crystal planes within the wafer. Consequently, perfect overlay accuracy is an impossible goal, and the fabrication industry has moved away from the technique known as "one-to-one" imaging, in which a full wafer is exposed in a single step, to systems that expose only a portion of the wafer at a time. These systems are known as "step and repeat" or "direct step on" systems, and involve the projection of only a single circuit die, or a small number of dies, at one time, with alignment being performed prior to each exposure.
With this background, it will be appreciated that there has been a significant need in the field of electon image projection systems for a technique for aligning a projected electron image with a wafer that is to be exposed on a step-and-repeat basis. Prior alignment systems can do this only at the expense of reductions in useable wafer area. Electron image projection provides a higher resolution than is available from optical techniques. However, the high resolution of electron image projection cannot be fully utilized unless mask patterns from one lithography level to the next can be accurately overlaid. Prior to this invention, there has been no technique for accurate alignment in electron image projection systems used on a subfield or step-and-repeat basis.